The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device, which generates an output enable signal in synchronization with a DLL clock signal, and a method for driving the same.
Synchronous memory devices, e.g., double data rate (DDR) synchronous dynamic random access memory (SDRAM), are designed to generate a plurality of output enable signals in synchronization with a DLL clock signal (CLK_DLL) and having different pulse widths according to a burst length, and to selectively use one of them according to a column address strobe (CAS) latency.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, an internal command signal generator 10 receives external command signals to generate a plurality of internal command signals according to their combination. Examples of the external command signals include a chip select signal CS, a write enable signal WE, a row address strobe signal RAS, a column address strobe signal CAS. Examples of the internal command signals include an internal read command signal IRDP. The internal read command signal IRDP contains information on period (tCK) of an external clock signal CLK_EXT and is a pulse signal activated in response to an external read command (RD).
The synchronous semiconductor memory device such as a DDR SDRAM transfers data to other external devices using a delay locked loop (DLL) clock signal (CLK_DLL) produced by delaying a clock signal CLK_EXT inputted from an external device such as a memory controller. Such a clock synchronization circuit includes a phase locked loop (PLL) and a delay locked loop (DLL). The DLL is widely used in semiconductor devices because it has low noise and can be implemented in a small area compared with the PLL.
FIG. 2 is a block diagram of the DLL 20 illustrated in FIG. 1.
Referring to FIG. 2, the DLL 20 includes a clock buffer 21, a first delay line 23, a second delay line 22, a duty cycle corrector 24, a delay replica model 25, a phase comparator 26, and a delay controller 27. The clock buffer 21 buffers an external clock signal CLK_EXT and an external clock bar signal CLKB_EXT to generate a reference clock signal CLK_REF. The external clock bar signal CLKB_EXT is a clock signal having an opposite phase to the external clock signal CLK_EXT. The second delay line 22 delays the reference clock signal CLK_REF corresponding to the external clock signal CLK_EXT in response to a control signal CTR. The first delay line 23 delays a clock signal produced by buffering the external clock bar signal CLKB_EXT in response to the control signal CTR. The duty cycle corrector 24 corrects duty cycles of output signals of the first and second delay lines 23 and 22 to generate rising and falling DLL clock signals RCLK_DLL and FCLK_DLL. The delay replica model 25 delays the DLL clock signal RCLK_DLL through delay elements located in a clock path to generate a feedback clock signal CLK_FDB. The phase comparator 26 compares a phase of the reference clock signal CLK_REF with that of the feedback clock signal CLK_FDB. The delay controller 27 generates the control signal CTR according to an output signal of the phase comparator 26.
The rising DLL clock signal RCLK_DLL has a phase equal to that of the external clock signal CLK_EXT, the falling DLL clock signal FCLK_DLL has a phase opposite to that of the external clock signal CLK_EXT. For convenience, the DLL will be described, centering on the external clock signal CLK_EXT and the rising DLL clock signal RCLK_DLL.
The DLL 20 generates the rising DLL clock signal RCLK_DLL by compensating a clock delay component occurring while the rising DLL clock signal RCLK_DLL is transferred to a data output terminal of the semiconductor memory device, so that signals used for an input/output of a final data can be synchronized with the external clock signal CLK_EXT.
Referring again to FIG. 1, an output enable signal generator 30 receives the CAS latency CL, the burst length BL, the internal read command signal IRDP, and the rising DLL clock signal RCLK_DLL to generate output enable signals OE0, OE1, OE1.5, . . . , OEN, where n is a natural number or (natural number+0.5).
In other words, the internal read command signal IRDP is a pulse signal that is activated in response to the read command, and the output enable signal OE0 is a signal that is activated after a predetermined time elapses from the activation of the internal read command signal IRDP. The output enable signal OE0 has a pulse width corresponding to the burst length BL. The output enable signals OE1, OE1.5, . . . , OEN are signals that are produced by shifting the output enable signal OE0. The output enable signals OE1, OE1.5, . . . , OEN, except the output enable signal OE0, are signals that are activated in synchronization with rising or falling edges of the rising DLL clock signal RCLK_DLL. Generally, the output enable signal generator 30 is designed to generate a plurality of output enable signals OE1, OE1.5, . . . , OEN in synchronization with the rising or falling edges of the rising DLL clock signal RCLK_DLL, such that the output enable signals can be selectively used according to the CAS latency CL.
FIG. 3 is a block diagram of the output enable signal generator 30 illustrated in FIG. 1.
Referring to FIG. 3, the output enable signal generator 30 includes a delay option unit 31, an OE0 generating unit 32, an OE1 generating unit 33, an OE1.5 generating unit 34, . . . , and an OEN generating unit 35. The delay option unit 31 receives the rising DLL clock signal RCLK_DLL and the CAS latency CL to tune the rising DLL clock signal RCLK_DLL according to the CAS latency CL. The OE0 generating unit 32 receives the internal read command signal IRDP and the burst length BL to generate the output enable signal OE0. The OE1 generating unit 33 receives the output enable signal OE0 and an output signal TN_RCLK_DLL of the delay option unit 31 to generate the output enable signal OE1. The OE1.5 generating unit 34 receives the output enable signal OE1 and the output signal TN_RCLK_DLL of the delay option unit 31 to generate the output enable signal OE1.5. Likewise, the OEN generating unit 35 generates the output enable signal OEN. The OE1 to OEN generating units 32, 33, 34, . . . , 35 perform a reset operation in response to a reset signal OE_RESTB.
The delay option unit 31 includes a plurality of delay elements and a plurality of option circuits in order for the tuning operation. The delay option unit 31 is provided for a domain crossing of the external clock signal CLK_EXT and the rising DLL clock signal RCLK_DLL. The domain crossing is a conversion from a receiver domain to a transmitter domain. That is, the domain crossing is a conversion from a domain in which the read command is recognized to a domain in which data is outputted in synchronization with the external clock signal CLK_EXT. The domain crossing will be described later with reference to FIGS. 5 and 6.
FIGS. 4A and 4B are circuit diagrams of the OE1 generating unit 33 and the OE1.5 generating unit 34, respectively.
Referring to FIG. 4A, the OE1 generating unit 33 includes a transfer gate TGA, a first latch 41, and a first inverter INV1. The transfer gate TGA transfers the output enable signal OE0 to the first latch 41. The first latch 41 latches an output signal of the transfer gate TGA and is reset by the reset signal OE_RESTB. The first inverter INV1 drives an output signal of the first latch 41 to output the output enable signal OE1. The transfer gate TGA is enabled during a period in which the output signal TN_RCLK_DLL of the delay option unit 31 has a logic high level.
Referring to FIG. 4B, the OE1.5 generating unit 34 includes a transfer gate TGB, a second latch 42, and a second inverter INV2. The transfer gate TGB transfers the output enable signal OE1 to the second latch 42. The second latch 42 latches an output signal of the transfer gate TGB and is reset by the reset signal OE_RESTB. The second inverter INV2 drives an output signal of the second latch 42 to output the output enable signal OE1.5. The transfer gate TGB is enabled during a period in which the output signal TN_RCLK_DLL of the delay option unit 31 has a logic low level.
The OE2 generating unit (not shown), . . . , the OEN generating unit 35 have the same configuration as the OE1 generating unit 33 of FIG. 4A, except that the output enable signal generated from the previous stage is inputted to the next stage. An OE2.5 generating unit (not shown), an OE3.5 generating unit (not shown), etc. have the same configuration as the OE1.5 generating unit 34 of FIG. 4B, except that the output enable signal generated from the previous stage is inputted to the next stage.
FIGS. 5 and 6 are timing diagrams illustrating the tuning operation of the delay option unit 31 during the domain crossing.
In FIGS. 5 and 6, it is assumed that it takes 15 ns to output the internal data to the external circuit after the input of the read command in the same semiconductor memory device. In FIG. 5, the period tCK of the external clock signal CLK_EXT is 2.5 ns, the CAS latency CL is 6, the delay time of the delay replica model 25 is 2 ns, and the delay time locked after the locking at the second delay line 22 is 0.5 ns. In FIG. 6, the period tCK of the external clock signal CLK_EXT is 5 ns, the CAS latency CL is 3, the delay time of the delay replica model 25 is 2 ns, and the delay time locked after the locking at the second delay line 22 is 3 ns.
Referring to FIG. 5, the internal read command signal IRDP is generated after a predetermined time from the input of the read command RD. The OE0 generating unit 32 of FIG. 3 receives the internal read command signal IRDP to generate the output enable signal OE0. The pulse width of the output enable signal OE0 is determined by the burst length BL. The output enable signal OE1 is generated in synchronization with a time point 1 of the rising DLL clock signal RCLK_DLL, and the output enable signal OE2 is generated in synchronization with a time point 2 of the rising DLL clock signal RCLK_DLL. The output enable signal OE3 is generated in synchronization with a time point 3 of the rising DLL clock signal CLK_DLL, and the output enable signal OE4 is generated in synchronization with a time point 4 of the rising DLL clock signal RCLK_DLL. The output enable signal OE4.5 is generated in synchronization with a time point 4.5 of the rising DLL clock signal RCLK_DLL.
Meanwhile, the reference clock signal CLK_REF is the buffered external clock signal and is substantially equal to the external clock signal CLK_EXT. The rising DLL clock signal RCLK_DLL is produced by delaying the reference clock signal by “D1” at the second delay line 22 of FIG. 2. In other words, a time point 5 of the rising DLL clock signal RCLK_DLL corresponds to a time point delayed by “D2” at the delay replica model 25 of FIG. 2, that is, a time point 5 of the reference clock signal CLK_REF. In addition, since the reference clock signal CLK_REF is substantially equal to the external clock signal CLK_EXT, the time point 5 of the reference clock signal CLK_REF is substantially equal to the time point 5 of the external clock signal EXT_CLK. When the CAS latency CL is 6, data D0 exactly synchronizes with the time point 5 of the external clock signal CLK_EXT, that is, a sixth external clock signal CLK_EXT after the input of the read command RD. Subsequently output data D1, D2 and D3 exactly synchronize with the external clock signal CLK_EXT.
In FIG. 6, the period tCK of the external clock signal CLK_EXT is 5 ns, the CAS latency CL is 3, the delay time “D2” of the delay replica model 25 is 2 ns, and the second delay line 22 of FIG. 2 has the delay time of “D3” so as to output data in 15 ns. That is, a time point 2 of the rising DLL clock signal RCLK_DLL corresponds to a time point 2 of the reference clock signal CLK_REF, and it is substantially equal to a time point 2 of the external clock signal CLK_EXT. When the CAS latency CL is 3, data D0 exactly synchronizes with the time point 2 of the external clock signal CLK_EXT, that is, a third external clock signal CLK_EXT after the input of the read command RD. Subsequently outputted data D1, D2 and D3 exactly synchronize with the external clock signal CLK_EXT.
Meanwhile, the internal read command signal IRDP is generated after a predetermined time elapses from the input of the read command RD. The OE0 generating unit 32 of FIG. 3 receives the internal read command signal IRDP to generate the output enable signal OE0. The output enable signal OE1 is generated in synchronization with the time point 0 of the rising DLL clock signal RCLK_DLL in FIG. 6, while the output enable signal OE1 is generated in synchronization with the time point 1 of the rising DLL clock signal RCLK_DLL in FIG. 5. The output enable signals generated after the output enable signal OE1 also synchronize with the rising DLL clock signal RCLK_DLL at the time points different from those of FIG. 5.
Therefore, the tuning for the domain crossing must be performed using the delay option unit 31. For example, the output enable signal OE1 must be generated such that it always synchronizes with the time point 1 of the rising DLL clock signal RCLK_DLL. That is, the output enable signal OE1 synchronizes with the time point 1 of the rising DLL clock signal RCLK_DLL by further delaying it by “D4” through the domain crossing. Therefore, the output enable signal OE2 is also synchronized with the time point 2 of the rising DLL clock signal RCLK_DLL.
The delay option unit 31 for the tuning must be configured using a plurality of delay elements and a plurality of option circuits. In addition, as the period tCK of the external clock signal CLK_EXT decreases, a more precise control is needed. Consequently, a larger number of delay elements and option circuits are required.